1. Field of the Invention
The present invention relates to a structure useful for testing integrated circuit devices. More particularly, the present invention relates to apparatus and methods for testing integrated circuit devices using a structure for coupling probes of a probe device to corresponding electrical contacts on a product substrate.
2. Description of Related Art
Integrated circuit (IC) devices are normally tested to verify electrical functionality, and certain devices require high-temperature burn-in testing to accelerate early life failures of these devices. Typically, the testing is carried out by contacting connections on the IC devices with one or more testing apparatus. The testing can include testing to assess the functioning of elements of the IC devices as well as the integrity of the structure making up the connections and elements. IC devices are typically tested in wafer form, for example, using a wafer probing system, to separate non-defective chips from defective ones prior to dicing of the wafers into chip areas.
The various types of interconnection methods used to test IC devices include permanent, semi-permanent, and temporary attachment techniques. The permanent and semi-permanent techniques that are typically used include soldering and wire bonding to provide a connection from the IC device to a substrate with fanout wiring or a metal lead frame package. The temporary attachment techniques include rigid and flexible probes that are used to connect the IC device to a substrate with fanout wiring or directly to the test equipment.
Wafer probing is the process of electrically testing each die on a wafer. The probes of a probe device are placed on designated pads on the die, and a tester applies power to the power pads, injects a series of signals into the input pads, and monitors the corresponding signals returned from the output pads. Advanced wafer probing systems are capable of mapping the defective dice on a wafer, including relating the position of the die on the wafer to the failure modes observed.
One conventional type of probe card uses cantilevered arms extending obliquely outwardly from the planar surface of a substrate or a printed circuit board. Another type of probe card uses micro spring probes, eliminating the need for cantilevered arms, but having inherent limitations, such as peripheral probing only and limited pin count due to the size and locations of the springs. Cobra probes are another type of probe card used to test IC devices.
Cobra probes, which are a type of compliant interposer probe, have been used to test IC devices in IBM for many years. Cobra probe cards typically demonstrate performance of up to one million touchdowns. Cobra probes have primarily been used to test IC devices with C4 (Controlled Collapse Chip Connection) solder ball connections, but can be modified to test IC devices with wire bond pads. For example, cobra probes that have been found to be satisfactory for testing IC devices with C4 bumps are disclosed in U.S. Pat. No. 4,027,935 to Byrnes et al., entitled CONTACT FOR AN ELECTRICAL CONTACTOR ASSEMBLY, which is assigned to the common assignee of the present application.
FIG. 1 is a cross-sectional view of a conventional apparatus for testing integrated circuit devices, in an operative position. Referring to FIG. 1, the apparatus 100 includes a probe device 120, a ceramic substrate 130, and a printed circuit board (not shown) coupled to the ceramic substrate 130. During wafer-level testing, the probe device 120 is electrically coupled to the ceramic substrate 130. Wafer probing is typically done on a single chip site. For example, a wafer 110, which is supported by a chuck (not shown), is moved to an operative position such that the tips of the probes 125 make contact with the electrical contacts 115 of a chip D2 of the wafer 110.
The entire probe device 120 or tips of the probes 125 may be made of a high-strength metal such as tungsten to resist damage from use. Even under ideal circumstances, the IC device under test, e.g., chip D2 contact pads, typically receives some damage from the probe tip touchdown.
FIG. 2 is a top view that shows a portion of a conventional ceramic substrate for use in testing integrated circuit devices. Referring to FIG. 2, the ceramic substrate 200, which may be a multi-layer ceramic (MLC), includes an array of electrical contacts disposed on a first surface thereof. For example, the array of electrical contacts includes electrical contacts 212 and 263, which are in design positions on the ceramic substrate 200. During high-temperature processing of ceramic substrates, electrical contacts tend to change position. As a result, the positionally inaccurate electrical contacts, e.g., electrical contacts 220 and 260, are positioned such that at least portions thereof are not aligned to design positions on the ceramic substrate 200. As shown in FIG. 1, certain probes 125 of the probe device 120 are not electrically connected to the electrical contacts 135 of the ceramic substrate 130, e.g., the positionally inaccurate electrical contacts 220 and 260 of FIG. 2. Ceramic substrates for use in testing integrated circuit devices are generally expensive to fabricate and the electrical contacts thereon only last a certain number of testing operations.